• What is VLSI?
• Evolution of IC design and fabrication
• ASIC vs FPGA Design
• Overview of the complete VLSI design flow: Specification → Design → Verification → Fabrication
• Design abstraction levels: Behavioral, RTL, Gate, and Layout

• Boolean Algebra and Logic Gates
• Combinational and Sequential Circuits
• Flip-Flops, Counters, Multiplexers, Decoders, etc.
• CMOS Logic: Inverter, NAND, NOR Design

Power, Delay, Noise Margin, and Sizing Concepts

• Introduction to HDL and RTL design
• Verilog Syntax, Modules, Operators, and Constructs
• Sequential and Combinational Circuit Modeling
• FSM Design and Implementation
• Overview of SystemVerilog for Advanced RTL
• Design Simulation and Debugging

• What is Verification?
• Types of Verification: Static vs Dynamic
• Testbench Architecture & Stimulus Generation
• Writing Self-Checking Testbenches
• Introduction to Assertions
• Coverage Metrics (Code, Functional, Toggle)
  
  
• SystemVerilog for Verification – Classes, Constraints, Interfaces

• RTL to Gate Level Conversion
• Synthesis Tools and Flow
• Setup & Hold Timing, Slack, and Timing Paths
• Static Timing Analysis (STA) Basics
• Scan Chain Insertion and ATPG

Boundary Scan, BIST Techniques